Conventional integrated circuit (IC) simulation tools implement layout data in a graphics data syntax (.gds) file extension format and typically call for the design to be design rules check (DRC) and layout versus schematic (LVS) clean. Conventional IC simulation tools also implement a netlist. The IC design will usually be finished and the layout complete before a voltage drop issue can be uncovered. This can be too late to permit an efficient design process. If the conventional tool is operated in a DC mode, the calculated and reported voltage drop of the IC power mesh will be over estimated since on-chip capacitance will not be considered. The voltage drop of the bond wire and package will be underestimated since the package and bond wire instantaneous voltage drop is a function of the instantaneous current change (i.e., dI/dT) which depends on the package and bond wire inductance. In a DC simulation, dI/dT is simulated as zero and the inductive effects are ignored. If an AC vector based simulation is executed, the capacitance and inductance can be evaluated. However, the simulation (i) can take several days to complete, (ii) will be extremely CPU intensive, and (iii) in some cases, is not practical. For most IC designs, conventional commercial simulations are not practical. Conventional tools (i) do not use voltage controlled current sources and (ii) overestimate the instantaneous voltage drop. As the core voltage drops, transistor gate and drain voltages drop and the output drive current is reduced. The drop in gate and drain voltages and drive current can cause inaccurate simulation results.
It would be desirable to have a method and/or architecture for simulating integrated circuit performance that provides (i) instantaneous voltage drop sensitivity analysis, (ii) simulation of on-chip capacitance and wire-bond inductance, and/or (iii) implementation independently of the circuit .gds file and/or netlist.